Development of micro-strip gas chamber for neutron scattering; Development and simulation of encode board

Masaoka, Sei; Nakamura, Tatsuya; Yamagishi, Hideshi; Soyama, Kazuhiko

JAERI-Research 2003-012, 14 Pages, 2003/06

JAERI-Research-2003-012.pdf:1.58MB

A micro-strip gas chamber (MSGC) using helium-3 gas has been developing as a two-dimensional position sensitive neutron detector for neutron scattering experiments in a high-intensity proton accelerator facility. We have developed the encode board that have built-in FPGAs (Field-Programmable Gate Array). Logics of FPGAs can be freely programmed to carry out digital processing of signals from MSGC and information of the tracks of protons and tritons can be obtained by the encode board. Therefore, the position of neutron capture (more properly the centra of the track) can be calculated by a series of data handling system. As the result of the simulation of a neutron detection experiment, it has proved that the position resolution of less than 1.6 mm can be obtained by using this data handling system.

FPGA utilization of the accelerator interlock system through MPS development in LIPAc

Nishiyama, Koichi; Takahashi, Hiroki; Sakaki, Hironao; Narita, Takahiro; Kojima, Toshiyuki*; Knaster, J.*; Marqueta, A.*

no journal, , 

The development of IFMIF(International Fusion Material Irradiation Facility) to generate a 14 MeV source of neutrons with the spectrum of DT fusion reactions is indispensable to qualify suitable materials for the First Wall of the nuclear vessel in fusion power plants. As part of IFMIF validation activities, LIPAc (Linear IFMIF Prototype Accelerator) facility, currently under installation at Rokkasho (Japan), will accelerate a 125 mA CW and 9 MeV deuteron beam with a total beam power of 1.125 MW. The Machine Protection System (MPS) of LIPAc provides an essential interlock function of stopping the beam in case of anomalous beam loss or other hazardous situations. High speed processing is necessary to achieve properly the MPS main goal. This high speed processing of the signals, distributed alongside the accelerator facility, is based on FPGA (Field Programmable Gate Array) technology. This paper describes the basis of FPGA use in the accelerator interlock system through the development of LIPAc.